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-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:31:44 05/21/2013 
-- Design Name: 
-- Module Name:    P1E - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.all;
use IEEE.NUMERIC_STD.all;

entity Registers is
    Port ( reg1_rd : in  STD_LOGIC_VECTOR (4 downto 0);
           reg2_rd : in  STD_LOGIC_VECTOR (4 downto 0);
           reg_wr : in  STD_LOGIC_VECTOR (4 downto 0);
           data_wr : in  STD_LOGIC_VECTOR (31 downto 0);
           clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           wr : in  STD_LOGIC;
           data1_rd : out  STD_LOGIC_VECTOR (31 downto 0);
           data2_rd : out  STD_LOGIC_VECTOR (31 downto 0));
end Registers;

architecture processor_arq of Registers is

type MEM is array (0 to 31) of STD_LOGIC_VECTOR (31 downto 0);
signal reg : MEM;
signal i : integer;

begin

	process(clk, reset, wr)
	begin

		if (reset = '1') then
			-- Enviamos el reset a los 32 registros
			for i in 0 to 31 loop 
				reg(i) <= (others => '0');
			end loop;
		elsif (falling_edge(clk) and wr = '1') then
			reg(TO_INTEGER(unsigned(reg_wr))) <= data_wr;
		end if;
	
	end process;
	
	data1_rd <= (others => '0') when (reg1_rd = "00000") else reg(TO_INTEGER(unsigned(reg1_rd)));
	data2_rd <= (others => '0') when (reg2_rd = "00000") else reg(TO_INTEGER(unsigned(reg2_rd)));

end processor_arq;

